 Research
 Open access
 Published:
Design of canonical signed digit multiplier using spurious power suppression technique adder
Journal of Engineering and Applied Science volume 70, Article number: 86 (2023)
Abstract
Reducing power consumption is a major challenge in developing integrated processors for smart portable devices. This is particularly important for extending battery life and ensuring extended usage of the device. However, some DSP processing applications involve complex algorithms that consume more power, which poses a significant challenge in designing DSP applications for VLSI circuits. To address this issue, lowpower consumption methodologies are required. Although various strategies have been developed to reduce power consumption, they have not demonstrated a significant decrease in dynamic power consumption, which is the primary factor determining the total amount of power dissipation.
The focus of this research is to develop a lowpower multiplier using the spurious power suppression technique (SPST), a method that divides the arithmetic unit into the most significant part (MSP) and least significant part (LSP) and turns off the MSP when it is not required for computation. This approach reduces dynamic power and overall power consumption of the VLSI combinational circuit. The proposed system also utilizes canonical signed digit (CSD) representation to further reduce power usage.
The system was designed using Cadence design suite, and the results showed a significant reduction of 35.8% in power consumption for a 32bit SPSTenabled CSD multiplier. The proposed system’s total power consumption is 0.561 mW. Additionally, the proposed system was used in a power and areaefficient 256point FFT architecture, resulting in an 86.6% reduction in power consumption. This system is suitable for realtime applications such as systems that use orthogonal frequency division multiplexing.
Introduction
Multiplication is a fundamental arithmetic operation and plays a significant role in digital signal processing (DSP) applications. In the multiplier, partial products obtained through the multiplication process are added using adders. However, as the number of partial products increases, more adders are required, resulting in increased power consumption. Thus, with technological advancements, the need for lowpower multipliers has arisen [10]. To achieve this, lowpower techniques are employed to reduce the number of partial products effectively while also decreasing power consumption. Most lowpower techniques aim to reduce dynamic power usage by dividing the arithmetic unit into two sections, most significant part (MSP) and least significant part (LSP), and turning off the noneffective component during partially guarded computation (PGC) to save power. Experimental findings have shown that the PGC approach reduces power consumption by 10–44% in array multipliers. Another lowpower design approach involves checking and carrying out the functional unit addition operation, scaling the resultant total to equal the initial length. The simulation’s findings demonstrate that lowpower adders perform computations more effectively than traditional adders. A lowpower multiplier design that reduces the switching activity of partial products by using the booth algorithm (Radix 4) results in lowpower consumption with increased delay and area. Glitch power can be reduced by changing current gates to ones that have a control input, shortening the settling time to reduce minimum power downtime after reactivation. The proposed system employs two techniques: canonical signed digit and spurious power suppression technique (SPST). Canonical signed digit reduces the number of nonzero digits in a number, thereby reducing the number of partial products. SPST divides the two Nbit binary number into MSP and LSP, computing MSP results only when the computation’s results are affected, lowering the dynamic power, and reducing the overall power consumption of the VLSI combinational circuit [1].
Related work
A novel technique selectively activates components within functional units based on the input data, effectively reducing unnecessary power consumption. The findings and experimental results highlight the potential of partially guarded computation in achieving significant power savings while maintaining system performance. This work serves as an important reference for researchers and practitioners in the field of lowpower electronics design, guiding the development of energyefficient solutions for modern electronic systems. In their work, Choi, Jeon, and Choi focused on power minimization of functional units through partially guarded computation. They presented their findings at the IEEE International Symposium on Low Power Electronics Design in 2000. The authors introduced a technique that aimed to reduce power consumption by selectively activating functional units only when necessary. By employing this approach, they achieved significant power savings in the design of functional units. The paper provides detailed insights into the methodology and experimental results obtained, showcasing the effectiveness of their proposed technique [2]. Chen, Sheen, and Wang presented a lowpower adder design that operates on effective dynamic data ranges. Their work, published in the IEEE Transactions on Very Large Scale Integration (VLSI) Systems in 2002, aimed to reduce power consumption in adder circuits. The authors introduced an innovative approach that utilizes dynamic data ranges to optimize the adder’s power efficiency. By adjusting the data range dynamically based on the input operands, the proposed adder achieved significant power savings while maintaining accuracy. The paper provides a comprehensive analysis of the design methodology, experimental results, and comparative evaluations with other adder architectures [3]. In the study titled “Minimization of switching activities of partial products for designing lowpower multipliers,” the authors developed a lowpower design technique that focuses on minimizing the switching activities of partial products. They examined the switching activities of several partial product generation systems and identified the factors that influenced power usage. The proposed method is a modified partial product generation technique that lowers switching activities [4]. The authors of the study “Glitch power minimization by selective gate freezing” developed a method to reduce glitch power consumption in digital circuits by selectively freezing specific gates. Glitches are shortlived, undesired voltage changes that occur in combinational circuits when logic gates are switched. These glitches can waste a large amount of power, increasing the circuit and overall power usage. The proposed algorithms identify the gates that should be frozen based on their glitchgenerating behavior [5]. In their work, Benini et al. proposed a technique called selective gate freezing for glitch power minimization. Published in the IEEE Transactions on Very Large Scale Integration (VLSI) Systems in 2000, the authors addressed the issue of power consumption in digital circuits due to glitches. They introduced a novel approach that selectively freezes certain gates in the circuit during inactive periods, reducing dynamic power dissipation. The paper presents a detailed analysis of the methodology, experimental results, and comparisons with existing glitch power reduction techniques. The findings highlight the effectiveness of selective gate freezing in achieving significant power savings while maintaining circuit functionality [6]. Henzler et al. presented a fast powerefficient circuitblock switchoff scheme in their publication in Electronics Letters in 2004. The authors addressed the power consumption issue in integrated circuits by proposing a technique that selectively switches off circuit blocks during periods of inactivity. By employing a fast switchoff mechanism, the proposed scheme achieved power savings by reducing leakage and dynamic power dissipation. The paper provides a concise explanation of the technique along with experimental results demonstrating its effectiveness in reducing power consumption. Comparative evaluations with other power reduction schemes further emphasize the advantages of the proposed circuitblock switchoff scheme [7]. Lakshmi et al. proposed a design technique for lowpower multipliers by employing the spurious power suppression technique (SPST). The authors addressed the challenge of power consumption in multiplier circuits and introduced an innovative approach to mitigate spurious power dissipation. The SPST method effectively suppressed power consumption by identifying and reducing unnecessary power dissipation caused by various sources, such as glitching and leakage currents. The paper presents a comprehensive explanation of the design methodology, experimental results, and comparative evaluations with conventional multiplier architectures. The findings highlight the effectiveness of the SPST technique in achieving substantial power savings while maintaining the desired functionality of the multiplier circuit [1].
Proposed method
Figure 1 shows the block diagram of an SPSTenabled CSD multiplier. The inputs, A and B, are both 16bit numbers. The partial product candidate generator block takes in input A and generates three partial product candidates, with values of − A, 0, and A, each having 32 bits. The CSD recoder output provides magnitude and sign data, which are used to select one of these partial products. The 16bit input B is recoded by the CSD recoding block to produce 17bit magnitude and sign values. Depending on these values, 17 partial products are created, and one is chosen for further processing. The selection of the partial product is based on the nonzero magnitude values from the CSD block. Seventeen partial products are then generated, of which only nine are chosen. The chosen partial products, except for the ninth one, are provided to the SPST adder, with two of them being supplied back to back. The shifting block left shifts the remaining 16 partial products. The conventional adder receives the outputs from the four SPST adders and provides the final result.
CSD recoding block
The canonical signed digit is one type of number representation used for arith metic operations. It is also known as a recoding technique since it will recode the original number to create a new one with a minimum amount of nonzero digits. This method guarantees that the average number of nonzero digits will never be greater than n/2. The canonical signed digit (CSD) representation is distinct because consecutive nonzero digits are one of the key properties of the CSD [8].
The CSD recoding circuit is constructed to take benefit of this property by converting three input bits into a single CSD digit, as shown in Fig. 2. The converter recodes three binary digits, i.e., b_{i+1}, b_{i}, and b_{i−1}, into a single CSD digit x_{i} which is represented in terms of magnitude bit x_{i,m} and sign bit x_{i,s}. In the signmagnitude encoding, 0.1 and − 1 are represented as 00, 01, and 11, respectively. Additionally, two bypass signals are employed, namely input bypass signal p_{i} and output bypass signal p_{i+1}. The truth table for binary to CSD conversion is shown in Table 1. It can be seen that when p_{i} = 0, a single CSD digit x_{i} and the new bypass signal for the following procedure are formed from the three binary digits b_{i+1}, b_{i}, and b_{i−1}. The magnitude bit x_{i,m} has the same value as the output bypass signal p_{i+1}. The magnitude bit is determined by the value of b_{i} and b_{i−1}, while the sign bit is impacted by b_{i+1} and x_{i,m}. Regardless of the inputs, all outputs become zeros when p_{i} = 1. Therefore, in this instance, the converter’s inputs are ignored or bypassed, generating the next process’s bypass signal p_{i+1} with the value zero [9].
The 16bit CSD recoding block is shown in Fig. 3. The 17bit CSD representation of the input is generated by this circuit in the form of 17bit magnitude values and 17bit sign values. The single CSD digit binary to CSD conversion circuit used by the recoding block produces the sign bit and magnitude bit.
SPST adder
Figure 4 shows the cause for the spurious signal transitions. It is clear from the first and second cases that adding the two operands has no effect on the MSP outcome, whether or not there is a carry from LSP. Results for MSP can be expected from the sum achieved in both circumstances.
Eliminating the computation of MSP of operands can lead to a reduction in switching activities in related components, which subsequently lowers power consumption in the adder stage and minimizes glitching noises. In this study, an SPST adder has been developed that divides the adder into two sections and freezes the MSP input data if it does not affect the final sum. A detection logic circuit has been devised to identify the effective range of input and determine whether MSP results are influencing the calculation outcome. The Boolean expression used to design this logic circuit is displayed below:
Where A[m] is the m^{th} bit of the operand A and B[n] is the n^{th} bit of the operand B. A_{MSP} and B_{MSP} are the MSP part of the inputs A and B. When all of the bits in A_{MSP} and B_{MSP} are zeros,
A_{and} and B_{and} have zero values. The value of A_{nor} and B_{nor} is zero when all of the bits in A_{MSP} and B_{MSP} are ones. The detection logic unit will produce three output signals: Close, Carrctrl, and Sign. The MSP section will either be disabled or not, depending on the Close value. The MSP component is disabled to reduce power consumption if the Close is zero. This reduces the switching operations in the MSP section, resulting in zero dynamic power usage. The zero inputs are then sent to the MSP part. The MSP result obtained will be computed in the detection logic unit, and MSP bits are compensated by the Sign and Carrctrl signals.
The Boolean expression for the Sign and Carrctrl signals is obtained from the Karnaugh map as shown in Figs. 5 and 6. Using the eight possible combinations of the inputs A and B, the Sign, Carrctrl, Close, A_{and}, B_{and}, A_{nor}, and B_{nor} are generated which is shown in Table 2.
The expression of Carrctrl and Sign are derived from the Karnaugh map is given in Eqs. 7 and 8.
The detection logic circuit is shown in Fig. 7, and Fig. 8 shows the 32bit SPST adder design. The two 32bit inputs A and B in this design are split into the MSP and LSP.
The LSP adder computes the LSP independently. Latches are employed in the MSP component to control the inputs to the MSP adder designed with AND gates. If an MSP computation is required, the latches allow two MSP inputs to enter the adder; otherwise, they freeze the MSP inputs and permit the MSP adder to receive zero inputs. Moreover, the detection logic circuit receives these MSP inputs and employs them to determine whether to activate or deactivate the MSP.
The detected logic circuit enables the latches to provide MSP inputs to the MSP adder only if MSP computation is needed. On the other hand, if MSP computation is not needed, the detection logic circuit will disable the latch and provide zero inputs to the MSP adder. The resulting MSP sum will then be compensated by the sign extension circuit. The sign extension circuit receives three signals from the detecting logic circuit as inputs.
Partial product candidate generation based on CSD magnitude and sign values
The block diagram of this architecture features a partial product generator that takes in a 16bit input A and generates three possible partial products: A, 0, and − A. The sign and magnitude values produced by the CSD recoder block are utilized to select which of these 16bit partial products to use. Additionally, a second 16bit input (B) is fed into this block, which generates a 17bit recoded output represented in terms of 17bit magnitude and sign values. The output from the partial product generator block is 17, 16bit length partial products, as depicted in Fig. 9.
Selection of partial products block
In the previous design, 17 partial products of 16 bits each were generated and passed to the sign extension and shifting block. In this block, each partial product is extended to 32 bits using the sign extension method, which involves making the theoretical calculation of the multiplication process 32 bits long regardless of the actual length of the partial product obtained. During the multiplication process, all partial products except the first one are shifted by 1 bit. After sign extension, shifting operation is performed. The resulting partial products are then passed to the selection of partial products block, where only nine partial products out of the 17 are selected. This is because the CSD recoded output will have only n/2 nonzero values. Therefore, only those partial products whose sign values match the recoder output’s 01 and 11 are selected, as shown in Fig. 10.
Adding of partial products
After extracting the nine selected partial products, all except for the ninth one are fed into the SPST adder in pairs of two. The four resulting totals from the SPST adders are then passed into the two conventional adders, as illustrated in Fig. 11. To obtain the final result, the sum from the conventional adders is added to the ninth partial product using a traditional adder.
Power and areaefficient 256 FFT architecture
The fast Fourier transform (FFT) technique is a popular DSP method used to convert signals from the time domain to the frequency domain and vice versa. However, FFT involves a large number of multiplication operations, which can consume significant power. To address this issue, a power and areaefficient architecture for a 256point FFT can be developed by employing the SPSTenabled CSD multiplier technique, as illustrated in Fig. 12 [10]. In this architecture, the complex multiplier block utilizes an SPSTenabled CSD multiplier to perform the multiplication of the twiddle factors.
Results and discussion
The Verilog code for the SPSTbased CSD multiplier was implemented using Cadence with 90nm technology. Figures 13 and 14 depict the RTL design and the output waveform of the SPST adder, respectively. It can be observed from the waveform that the MSP computation is not performed during the negative cycle, even though the LSP output is present. Instead, MSP operations are carried out on the positive edge of the clock. As a result, the final sum is determined during the positive edge of the clock.
Table 3 presents the performance metrics of the SPST adder. On the other hand, Table 4 illustrates the dynamic power consumption of the MSP portion of the SPST adder and ripple carry adder. Notably, Table 4 reveals a remarkable reduction in dynamic power consumption for the MSP adder. This decrease is attributed to the exclusion of two ineffective input computations that the MSP adder does not add. Instead, the detecting logic unit of the SPST adder compensates for any obtained sum outcomes. As a result, unnecessary switching activity in the MSP is reduced, resulting in lower dynamic power consumption.
Figure 15 shows the output waveform for the signed multiplication for all signed input combinations. The performance parameters of the SPSTbased CSD multiplier are shown in Table 5. A total of 256point FFT architecture is implemented using SPSTenabled CSD multiplier. The FFT architecture is also implemented using Baugh Wooleymultiplier. The results obtained were compared, and it has been observed that SPSTenabled CSD multiplier consumes less power and area compared to BaughWooley multiplier. The results are shown in Table 6.
Conclusions
The canonical signed digit is a number representation commonly used in arithmetic operations, where the original number is recoded to produce a new one with the least possible number of nonzero digits. This method has the advantage of ensuring that the average number of nonzero digits is always less than or equal to n/2. The SPST adder incorporates both LSP and MSP adders in its design, with the MSP component turned off depending on the input’s dynamic range. This feature contributes to a reduction in dynamic power dissipation.
After deployment, the SPST adder demonstrated a significant reduction in dynamic power consumption. For an input combination consisting of 50% data and a dynamic range of 16 bits out of 32 bits, the power dissipation decreased by 38.5% compared to the carry ripple adder (with MSP adder enabled for 50% of input combinations). The proposed multiplier consumed 0.561 mW of power. Furthermore, the proposed system was applied to the power and areaefficient 256point FFT architecture, leading to an 86.6% reduction in overall power consumption compared to the same application using the BaughWooley multiplier.
Availability of data and materials
Not applicable.
Abbreviations
 SPST:

Spurious power suppression technique
 CSD:

Canonical signed digit
 FFT:

Fast Fourier transform
 MSP:

Most significant part
References
Lakshmi A, Kyung Tae Kim, Tanmayi M, Pavani K (2020) Design of lowpower multiplier using spurious power suppression technique (SPST). J Crit Rev 7(4)
Choi J, Jeon J, Choi K (2000) Power minimization of functional units by partially guarded computation. In: Proc IEEE Int Symp Low Power Electron Des. pp 131–36
Chen O, Sheen R, Wang S (2002) A lowpower adder operating on effective dynamic data ranges. IEEE Trans Very Large Scale Integr (VLSI) Syst 10(4):435–53
Chen O, Wang S, Wu YW (2003) Minimization of switching activities of partial products for designing lowpower multipliers. IEEE Trans Very Large Scale Integr (VLSI) Syst 11(3):418–33
Benini L, Micheli GD, Macii A, Macii E, Poncino M, Scarsi R (2000) Glitch power minimization by selective gate freezing. IEEE Trans Very Large Scale Integr (VLSI) Syst 8(3):287–98
Henzler S, Georgakos G, Berthold J, SchmittLandsiedel D (2004) Fast powerefficient circuitblock switchoff scheme. Electron Lett 40(2):103–104
Chen KH, Chu YS, Member (2009) A spurious power suppression technique for multimedia/DSP applications. IEEE Trans Circuits Syst Reg Pap 56(1):132
Vishwanath BR, Theerthesha TS (2015) Multiplier using canonical signed digit code. Int J Res Appl Sci Eng Technol (IJRASET) 3(V)
Faust F, Gustafsson O, Chang CH (2011) Fast and VLSI efficient binarytoCSD en coder using bypass signal. Electron Lett 47(1):18
Sagar M, Sayed Saber Ali, Sharath, Shashidhara NJ, Sharon Thomas, Vijay Ganesh PC (2016) Power and area efficient 256 FFT architecture
Acknowledgements
First and foremost, I would like to thank my college who give me a comfortable working and researching atmosphere. I am also greatly indebted to all my teams who have helped me to develop the fundamental and essential academic competence. My sincere appreciation also goes to all my colleagues, who are my proud of my life. Last but not least, I want to thank all my friends, for their encouragement and support.
Funding
Not applicable.
Author information
Authors and Affiliations
Contributions
The manuscript was written through contributions of all authors. And all authors have read and approved the manuscript, which is the case.
Corresponding author
Ethics declarations
Competing interests
The authors declare that they have no competing interests.
Additional information
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made. The images or other third party material in this article are included in the article's Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article's Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit http://creativecommons.org/licenses/by/4.0/. The Creative Commons Public Domain Dedication waiver (http://creativecommons.org/publicdomain/zero/1.0/) applies to the data made available in this article, unless otherwise stated in a credit line to the data.
About this article
Cite this article
K. P., J., Miranda, P.S. & Shri, K.A. Design of canonical signed digit multiplier using spurious power suppression technique adder. J. Eng. Appl. Sci. 70, 86 (2023). https://doi.org/10.1186/s44147023002540
Received:
Accepted:
Published:
DOI: https://doi.org/10.1186/s44147023002540