Table 3 Performance parameters of the SPST adder
From: Design of canonical signed digit multiplier using spurious power suppression technique adder
Performance parameters | SPST adder |
|---|---|
Area (µm2) | 2624 |
Power (nW) | 20,033.024 |
Delay (ps) | 6867 |
From: Design of canonical signed digit multiplier using spurious power suppression technique adder
Performance parameters | SPST adder |
|---|---|
Area (µm2) | 2624 |
Power (nW) | 20,033.024 |
Delay (ps) | 6867 |