Table 6 Comparison of power and area of modified system for signed multiplication
From: Design of canonical signed digit multiplier using spurious power suppression technique adder
Comparison of power and area of signed multiplier results | |||
|---|---|---|---|
Power and area-efficient 256 FFT archi tecture | Using Baugh-Wooley multiplier | Using SPST-enabled CSD multiplier | Percentage reduction in number of cells, area, and power |
Numbers of cells | 51,990 | 10,994 | 78.8% |
Power (mW) | 23.228 | 3.1 | 86.6% |
Area (µm2) | 367,019 | 70,070 | 80.9% |