Table 7 Implementation results of the ITEO method
From: FPGA implementation of an improved envelope detection approach for bearing fault diagnosis
Resource | Function | Used | Available | Percentage [%] |
|---|---|---|---|---|
LUT (lookup table) | Allows the implementation of complex logic functions | 8675 | 17,600 | 49.29 |
DSP slices (digital signal processing) | Efficiently perform mathematical operations usually used in signal processing | 60 | 80 | 75 |
BRAM (block RAM) | Provide a fast and efficient way to store data during FPGA operations | 37 | 60 | 61.67 |
LUTRAM blocks (lookup table RAM) | Provides faster access but is limited in size and suitable for smaller tables | 1862 | 6000 | 31.03 |
BUFG (buffered universal global clock buffer) | Used to distribute clock signals across different parts of the FPGA design | 1 | 32 | 3.13 |
FF blocks (flip-flop blocks) | Creating memory elements and storing states in an FPGA design | 13,133 | 35,200 | 37.31 |