Table 1 The temperature rises of the chip with different levels of computational grids
From: Multi-objective optimization of heat sink with multi-cross-ribbed-fins for a motor controller
Grid | Grid size | Grid level | The temperature rise of the chip ΔT (K) |
|---|---|---|---|
grid 1 | 0.85mm | 4.38 million | 38.14 |
grid 2 | 0.75mm | 5.81 million | 37.61 |
grid 3 | 0.6mm | 9.94 million | 37.72 |
grid 4 | 0.5mm | 14.91 million | 37.35 |
grid 5 | 0.4mm | 21.96 million | 37.32 |